Integrated downscale in video core
US9432614B2 · kind B2 · utility
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4References
18Claims
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Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Nov 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/33
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Implementations include video image processing systems, methods, and apparatus for integrated video downscale in a video core. The downscaler computes and writes a display frame to an external memory. This frame may have the same resolution as a target display device (e.g., mobile device). The target display device then reads this display frame, rather than the original higher resolution frame. By enabling downscale during encoding/decoding, the device can conserve resources such as memory bandwidth, memory access, bus bandwidth, and power consumption associated with separately downscaling a frame of video data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.