Method and apparatus for per core performance states
US9436254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2012 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Mar 16, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.