Patent · US Active

Saving power when in or transitioning to a static mode of a processor

US9436264B2 · kind B2 · utility

1Cited by

114References

21Claims

0Family size

Assignee

Intellectual Ventures Holding 81 LLC · US

Inventors

Andrew Read · Volbringen, DE
Sameer Halepete · San Jose, US
Keith Klayman · Sunnyvale, US

Key dates

Filing date	Jan 10, 2011
Grant date	Sep 6, 2016
Priority date	—
Expiry date	Feb 23, 2031

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.