Technique for live analysis-based rematerialization to reduce register pressures and enhance parallelism
US9436447B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2012 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Oct 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device compiler and linker within a parallel processing unit (PPU) is configured to optimize program code of a co-processor enabled application by rematerializing a subset of live-in variables for a particular block in a control flow graph generated for that program code. The device compiler and linker identifies the block of the control flow graph that has the greatest number of live-in variables, then selects a subset of the live-in variables associated with the identified block for which rematerializing confers the greatest estimated profitability. The profitability of rematerializing a given subset of live-in variables is determined based on the number of live-in variables reduced, the cost of rematerialization, and the potential risk of rematerialization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.