System and method for executing sequential code using a group of threads and single-instruction, multiple-thread processor incorporating the same
US9436475B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2012 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Apr 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/451
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for executing sequential code in the context of a single-instruction, multiple-thread (SIMT) processor. In one embodiment, the system includes: (1) a pipeline control unit operable to create a group of counterpart threads of the sequential code, one of the counterpart threads being a master thread, remaining ones of the counterpart threads being slave threads and (2) lanes operable to: (2a) execute certain instructions of the sequential code only in the master thread, corresponding instructions in the slave threads being predicated upon the certain instructions and (2b) broadcast branch conditions in the master thread to the slave threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.