Enhanced pre-fetch in a memory management system
US9436610B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2014 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Nov 5, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.