Method and apparatus for determining common node logical connectivity
US9436796B2 · kind B2 · utility
0Cited by
7References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 11, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Feb 11, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system, and computer-readable medium are described that enable efficient design processes for integrated circuits. In particular, tools are described which enable an integrated circuit designer to visualize an integrated circuit design without combinational logic and, from such visualization, identify locations in the design of common node logical connectivity. This information enables the designer to identify potential areas where the integrated circuit design can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.