Low latency synchronization scheme for mesochronous DDR system
US9437278B2 · kind B2 · utility
0Cited by
9References
24Claims
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Key dates
| Filing date | Aug 3, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Aug 3, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.