Chip package having a patterned conducting plate and method for forming the same
US9437457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2013 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Aug 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of conducting sections electrically separated from each other; a plurality of conducting pads disposed on an upper surface of the patterned conducting plate; a chip disposed on the conducting pads; a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; and an insulating support layer partially surrounding the conducting bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.