Method for manufacturing semiconductor device having a multilayer interconnection
US9437568B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2014 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Oct 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/05442
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.