Temperature compensation method for high-density floating-gate memory
US9437602B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2012 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Dec 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit (12) having a floating gate transistor (P3) operating in weak-inversion mode and a varactor (Cv) with a terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit (14) having a floating gate transistor (PI); a second current reference circuit (16) having a floating gate transistor (P2); and a control module (18) configured to selectively receive a reference current (I1, I2) from a drain of the floating gate transistor in each of the first and second current reference circuits. The control module operates to determine a ratio between the reference currents received from the first and second current reference circuits, generate a tuning voltage (Vx) in accordance with the ratio between the reference currents and apply the tuning voltage to the varactor in the memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.