Digital class-D amplifier and digital signal processing method
US9438182B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2012 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Oct 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/21196
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital class D amplifier (10) is disclosed, comprising a pulse width modulator (PW Mod) comprising: a digital loop filter (Loop F) adapted to receive an input signal (x[n]) and a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process at a clock frequency (f_s) said input and feedback signals for providing as output a filtered digital signal (w[n]); a PWM conversion module (PW_CM) having an input (24) for receiving the filtered digital signal (w[n]) and having a first output (25) connected to the digital loop filter (Loop F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output (25) the feedback signal (fb[n]). The PWM conversion module (PW_CM) comprises: a first comparator (CMP_N) adapted to compare the filtered digital signal (w[n]) with a first reference triangular waveform (VTn[n]) for providing as output a first PWM signal (yn[n]), the first reference triangular waveform having a frequency (f_osc) much lower than said clock frequency (f.s); a second comparator (CMP_P) adapted to compare the filtered digital signal (w[n]) with a second reference triangular waveform (VTp[n]) for…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.