High efficiency half-cross-coupled decoupling capacitor
US9438225B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Jun 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/212
Abstract
A decoupling capacitor circuit design facilitates high operational frequency without sacrificing area efficiency. In order to disassociate the sometimes opposing design criteria of high operational frequency and area efficiency, a p-channel field effect transistor (PFET) and an n-channel field effect transistor are connected in a half-cross-coupled (HCC) fashion. The HCC circuit is then supplemented by at least one area efficient capacitance (AEC) device. The half-cross-coupled transistors address the high frequency design requirement, while the AEC device(s) address the high area efficiency requirement. The design eliminates the undesirable trade-off between operating frequency and area efficiency inherent in some conventional DCAP designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.