Integrated circuits having low power, low interference and programmable delay generators therein and methods of operating same
US9438252B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Oct 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable delay generator includes a calibration circuit and a delay line responsive to a calibration control signal generated by the calibration circuit. The calibration circuit includes a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein. A frequency of the DCO is set by the calibration control signal. The delay line includes a second plurality of delay stages that are replicas of the first plurality of delay stages. The calibration circuit may include a current steering digital-to-analog converter (CSDAC), which is responsive to a digital calibration code, and a current-to-voltage converter, which is responsive to at least one current signal generated by the CSDAC. The DCO and other portions of the calibration circuit are disabled into a low power state upon completion of a calibration operation, which may commence upon start-up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.