High frequency delay lock loop systems
US9438255B1 · kind B1 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Jul 31, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.