Calibrated-output analog-to-digital converter apparatus and methods
US9438266B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2016 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Feb 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A direct current (“DC”) calibration reference voltage is applied at an input terminal of an N-level sigma-delta analog-to-digital converter (“ADC”). The ADC includes a current-mode DAC (“I-DAC”) operating as a feedback element. A count of logical 1s associated with each of N output levels is taken at outputs of a modulator portion of the ADC during a first mismatch measurement interval. Mismatch measurement logic subsequently transposes pairs of current sources between level selection switch matrices. Doing so causes modulator output error components resulting from mismatches between I-DAC current sources (“delta”) to appear as differential level-specific output counts. The mismatch measurement logic compares the differential counts to determine values of delta. The ADC then factors decimated modulator output counts by values of delta in order to correct for the I-DAC current source mismatch(es).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.