Clock circuit and method of operating the same
US9442510B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2015 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Mar 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock gating circuit includes a first transistor, a first inverter and a second transistor. A first terminal of the first transistor receives a clock input signal. A second terminal of the first transistor is coupled to a first node. The first transistor adjusts a voltage of the first node to a first voltage based on the clock input signal. The first inverter is coupled to the first node and receives the voltage of the first node, and outputs a clock output signal. A first terminal of the second transistor receives the clock input signal. A second terminal of the second transistor is coupled to the first node and a second node. The second transistor adjusts the voltage of the first node or the second node to the second voltage, based on the clock input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.