Minimizing bandwidth to track return targets by an instruction tracing system
US9442729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2013 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Feb 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3636
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device implementing minimizing bandwidth to track return targets by an instruction tracing system is disclosed. A processing device of the disclosure an instruction fetch unit comprising a return stack buffer (RSB) to predict a target address of a return (RET) instruction corresponding to a call (CALL) instruction. The processing device further includes a retirement unit comprising an instruction tracing module to initiate instruction tracing for instructions executed by the processing device, determine whether the target address of the RET instruction was mispredicted, determine a value of call depth counter (CDC) maintained by the instruction tracing module, and when the target address of the RET instruction was not mispredicted and when the value of the CDC is greater than zero, generate an indication that the RET instruction branches to a next linear instruction after the corresponding CALL instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.