Data processing apparatus and method for handling performance of a cache maintenance operation
US9442856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2015 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Jun 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.