Pixel circuit and display
US9443472B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Dec 12, 2013 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Mar 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0819
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel circuit and a display are configured to reduce the size of the pixel circuit, and in turn reduce the pixel pitch and increase the pixel number per unit area, and thus improve the display quality of pictures. The pixel circuit comprises a first pixel sub-circuit and a second pixel sub-circuit, and an initialization module (31) and a data voltage writing module (32) connected to the first pixel sub-circuit and the second pixel sub-circuit, wherein the initialization module (31) is connected to a reset signal terminal and a low level terminal, and is configured to initialize the first pixel sub-circuit and the second pixel sub-circuit under the control of a reset signal input at the reset signal terminal; and the data voltage writing module (32) is connected to a data voltage terminal and a gate signal terminal, and is configured, under the control of a signal input at the gate signal terminal, to firstly write a first data voltage to the first pixel sub-circuit and perform compensation for a driving module (331) of the first pixel sub-circuit, and then write a second data voltage to the second pixel sub-circuit and perform compensation for a driving module (332) of the second…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.