Programmable power for a memory interface
US9443572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2014 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Jun 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for delay control are described herein. In one embodiment, a delay system comprises a first delay circuit configured to provide a voltage bias to a second delay circuit, wherein the voltage bias controls a delay of the second delay circuit, and to update the voltage bias at an update rate. The delay system also comprises an update controller configured to adjust the update rate of the first delay circuit. For example, the update controller may adjust the update rate based on timing requirements of a memory interface incorporating the delay system. The update rate may be reduced when the timing requirements are more relaxed to reduce power, and may be increased when the timing requirements are tighter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.