Multi-level cell memory
US9443580B2 · kind B2 · utility
4Cited by
0References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2012 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Jun 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer structure comprising a split page buffer having a first page buffer and a second page buffer. The sensing circuit operates to read from the memory cell, places a first bit in one of the first page buffer and the second page buffer, and places the second bit in one of the first page buffer and the second page buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.