Method for capacitively reading resistive memory elements and nonvolatile, capacitively readable memory elements for implementing the method

US9443589B2 · kind B2 · utility

Assignees

• Forschungszentrum Jülich GmbH · DE
• Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen · DE

Inventors

• Stefan Tappertzhofen · Aachen, DE
• Eike Linn · Würselen, DE
• Lutz Nielen · Aachen, DE
• Rainer Waser · Aachen, DE
• Ilia Valov · Aachen, DE

Key dates

• Filing date: May 17, 2014
• Grant date: Sep 13, 2016
• Expiry date: May 17, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2213/79
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method for reading out a non-volatile memory element having at least two stable states 0 and 1. This memory element comprises at least one resistive memory cell, which encodes the two states 0 and 1 into a state HRS having higher electrical resistance and a state LRS having lower electrical resistance. In the two states 0 and 1, the memory element has differing capacitances C0,1; this difference is used to determine which state is present. A memory element is selected in which a fixed capacitance that is independent of the state of the memory cell is connected in series with the memory cell. A series connection of a resistive memory cell with a fixed capacitance, instead of with a second resistive memory cell, improves the signal strength during capacitive read-out. The second memory cell becomes indispensable for the memory function when the memory element is read out capacitively. Moreover memory elements were developed which combine a field effect transistor or a DRAM structure with a resistive memory cell or an antiserial series connection of such memory cells.