Semiconductor wafer, semiconductor IC chip and manufacturing method of the same
US9443808B2 · kind B2 · utility
1Cited by
0References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2014 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Oct 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer includes circuit integration regions each incorporating an integrated circuit and guard rings disposed to surround the circuit integration regions, respectively. A scribe region disposed between every adjacent two of the guard rings. An element and a pad electrically connected to the element are disposed in the scribe region. A groove is disposed along a corresponding guard ring on a front surface of the semiconductor wafer between the pad and the corresponding guard ring. The distance between the groove and the pad is varied along the corresponding guard ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.