Method of fabricating integrated circuits, integrated circuit component mask layout set, and component photomask set
US9443838B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2009 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Mar 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/50
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of fabricating integrated circuits includes the steps of: a) with reference to a physical design of a hardware unit, preparing an integrated circuit component mask layout set associated with component photomasks suitable for fabricating an array of the hardware units on a wafer; b) preparing the component photomasks with reference to the integrated circuit component mask layout set; c) forming the array of the hardware units and interconnections between adjacent hardware units on the wafer using the component photomasks prepared in step b) ; and d) cutting the wafer along selected ones of the scribe lines so as to form a plurality of integrated circuit dies. Each of the integrated circuit dies is independently selected from a single-type including only one of the hardware units, and a multi-type including a plurality of the hardware units that are interconnected electrically via uncut ones of the conductive paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.