Manufacturing method for an array substrate that can avoid electrical leakage of thin film transistors
US9443875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2014 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Apr 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/12
Abstract
The present invention provides array substrate and manufacturing method thereof and display device. The manufacturing method comprises: forming patterns including active regions of first and second TFTs by patterning process on substrate; forming gate insulation layer on the substrate; forming patterns including gates of the TFTs by patterning process on the substrate; forming isolation layer on the substrate; forming, on the substrate, second contacting vias for connecting sources and drains of the TFTs to respective active regions and first contacting via for connecting gate of the second TFT to source of the first TFT; and on the substrate, forming patterns of corresponding sources and drains on the second contacting vias above active regions of the TFTs, and meanwhile forming connection line for connecting gate of the second TFT to source of the first TFT above the first contacting via above gate of the second TFT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.