Thin film transistor substrate and the method thereof
US9443881B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2014 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Oct 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
Abstract
A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.