Method for manufacturing array substrate
US9443889B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Jul 17, 2015 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Jul 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for manufacturing an array substrate, wherein each data line in a plurality of data line groups forms an integral structure with a first shorting bar, and after etching a source-drain component to form a source electrode and a drain electrode, the data line groups which do not correspond to the first shorting bar is disconnected from the first shorting bar. By adopting the method provided by the present invention, electrostatic breakdown in the manufacturing process of the array substrate can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.