Correctable parity protected memory
US9444496B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Dec 10, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1056
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A correctable parity-protected memory system may include a parity-protected memory configured to hold dirty data, an error correction register configured to hold data, an exclusive-OR (XOR) circuit configured to exclusive-OR dirty data that is written into and removed from the parity-protected memory with the data in the error-correction register, and a controller. The controller may be configured to cause the results of the XOR circuit to accumulate in the error-correction register each time dirty data is written into and removed from the parity-protected memory, and, in response to detection of a fault in dirty data in the parity-protected memory, correct the fault based on the data in the error-correction register and dirty data in the parity-protected memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.