Integrated electrical and thermal solution for inverter DC-link capacitor packaging
US9445532B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2013 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Mar 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K7/20509
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An improved capacitor packaging solution is presented that incorporates both thermal and electrical considerations. A package can include capacitor elements electrically coupled to a bus bar, and a thermally enhanced isolation layer between the bus bar and a case. The isolation layer can be provided adjacent a case base and sidewall portions. The bus bar can be disposed adjacent the isolation layer and be configured to extend along the package side and along the package length below the capacitor elements to provide an extended path for heat dissipation from the bus bar prior to its contact with capacitor elements. The enhanced isolation layer is configured to conduct heat away from the bus bar to the case to avoid the hotspot temperature of the capacitor. Reduced capacitor temperature allows use of smaller, cheaper capacitors, reducing inverter costs without compromising performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.