Apparatus and method for implement a multi-level memory hierarchy

US9448879B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Theodros Yigzaw · Sherwood, US
• Oded Lempel · Zichron Ya'akov, IL
• Hisham Shafi · Beer Sheva, IL
• Geeyarpuram N. Santhanakrishnan · Mercer Island, US
• Jose A. Vargas · Rescue, US
• Ganapati Srinivasa · Portland, US
• Mohan J. Kumar · Beaverton, US
• Larisa Novakovsky · Haifa, IL
• Lihu Rappoport · Haifa, IL
• Chen Koren · Hadera, IL
• Julius Mandelblat · Haifa, IL
• Michael Mishaeli · Jerusalem, IL

Key dates

• Filing date: Dec 22, 2011
• Grant date: Sep 20, 2016
• Expiry date: Jan 29, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/1407
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.