Patent · US Active

Forward error correction with configurable latency

US9448885B2 · kind B2 · utility

0Cited by

4References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Wally Haas · St. John's, CA
Chuck Rumbolt · St. John's, CA

Key dates

Filing date	Jun 2, 2015
Grant date	Sep 20, 2016
Priority date	—
Expiry date	Jun 2, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/618
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm may continue to successively reduce the size of said buffer until the minimum number of buffer locations are utilized to achieve the target BER. If the buffer locations have been reduced such that the buffer size is too small and the target BER cannot be achieved, the algorithm may increase the size of the buffer until the minimum number of buffer locations are utilized to achieve the target BER.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.