Partition based design implementation for programmable logic devices
US9449133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2014 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Dec 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various techniques are provided to generate designs for programmable logic devices (PLDs). In one example, a computer-implemented method includes selectively grouping a first plurality of logic components for a first design into a plurality of partitions. The method also includes selectively merging at least a subset of the partitions of the first design. The method also includes converting each partition into a corresponding first physical implementation for a PLD. The method also includes comparing the first plurality of logic components to a second plurality of logic components for a second design to identify changed and unchanged partitions. The method also includes converting each changed partition into a corresponding second physical implementation for the PLD. The method also includes combining the first physical implementations for the unchanged partitions, with the second physical implementations for the changed partitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.