Parallel processor for providing high resolution frames from low resolution frames
US9449367B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2009 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Jul 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/0117
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Presented herein are caching structures and apparatus for use in block based video. In one embodiment, there is described a system receiving lower resolution frames and generating higher resolution frames. The system comprises an upsampling circuit, a first circuit, and a second circuit. The upsampling circuit upsamples a particular lower resolution frame, thereby resulting in an upsampled frame. The first circuit maps frames that are proximate to the particular frame, to the particular frame. The second circuit simultaneously updates the upsampled frame with two or more blocks from at least one of the frames that are proximate to the particular frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.