Circuit for memory write data operation
US9449663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Aug 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a supply voltage circuit, a voltage adjustment circuit, and a timing adjustment circuit. The supply voltage circuit is coupled to a memory device configured to provide a voltage level to the memory device during a write data operation. The voltage adjustment circuit is coupled to the supply voltage circuit, and is configured to provide at least one voltage level control signal to control one of a plurality of different voltages. At least one of the plurality of different voltages has a voltage level lower than a specified nominal supply voltage level. The timing adjustment circuit is coupled to the supply voltage circuit, and is configured to provide at least one voltage transition timing control signal to the supply voltage circuit. The supply voltage circuit is configured to provide at least one of the plurality of different voltages to the memory device during the write data operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.