Method and apparatus to detect LO leakage and image rejection using a single transistor
US9450537B2 · kind B2 · utility
3Cited by
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14Claims
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Key dates
| Filing date | Aug 25, 2014 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Oct 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/0408
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
LO leakage and Image are common and undesirable effects in typical transmitters. Typically, thirty complex hardware and algorithms are used to calibrate and reduce these two impairments. A single transistor that draws essentially no de current and occupies a very small area, is used to detect the LO leakage and Image Rejection signals. The single transistor operating as a square law device, is used to mix the signals at the input and output ports of the power amplifier (PA). The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.