Multi-bit error correction method and apparatus based on a BCH code and memory system
US9450615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Apr 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.