Method for testing a photonic integrated circuit including a device under test
US9453723B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2015 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Jun 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/12019
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method is for testing a photonic integrated circuit (IC) that includes a test structure having a test optical splitter, a test optical input, and first and second test optical outputs. A device under test (DUT) is coupled between the first test optical output and the first output of the test optical splitter. The deembedding structure includes a deembedding optical splitter, a deembedding optical input and first and second deembedding optical outputs. The method includes coupling a test probe device to the test optical inputs and outputs and the deembedding optical inputs and outputs and operating the test probe device to make at least one test measurement related to the DUT and at least one deembedding measurement. The at least one test measurement is processed with the at least one deembedding measurement to determine whether the DUT is acceptable and independent of alignment error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.