LDO regulator powered by its regulated output voltage for high PSRR
US9454168B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2015 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | May 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/007
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
In an LDO regulator, two feedback loops are created. The first feedback loop includes a high power PNP bipolar power transistor connected in series between the input voltage Vin terminal and the output voltage Vout terminal. The first feedback loop includes a first error amplifier that controls a drive transistor to drive the base of the power transistor such that Vout matches a set voltage Vset. This first feedback loop circuitry uses an operating voltage (the upper rail voltage) that is regulated by a second feedback loop and is approximately 300 mV greater than Vout. As a result, the control circuitry will be powered by a low ripple supply to improve output PSRR. Further, the power transistor is connected such that any noise in the input voltage is a common mode voltage across the base-emitter of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.