Pipelined processor
US9454376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2013 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Mar 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a processor with a multi-pipeline fetch structure or a multi-cycle cache structure, including: an integer core which reads instruction transmitted from a lower block, executes an operation corresponding to the instruction, and transmits an instruction address to the lower block; an instruction buffer which stores instruction data which are requested by the integer core by using the instruction address and transmits the instruction data in response to the request of the integer core; and an instruction cache which stores a portion of data of a program memory and transmit the data to the instruction buffer in response to the request of the instruction buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.