Error correction method and module for non-volatile memory
US9454428B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2014 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Apr 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is provided an error correction method for a non-volatile memory. The method includes receiving a codeword read from the non-volatile memory, computing a reliability information for each bit of the codeword received, and performing a reduced-complexity soft-decision decoding (SDD) technique to decode the received codeword. In particular, the SDD technique includes forming a set of test patterns based on the reliability data, and determining whether to perform a HDD of a test pattern in the set of test patterns based on a distance between the test pattern and a candidate pattern. There is also provided an error correction module for a non-volatile memory and a memory system incorporating the error correction module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.