Non-volatile logic based processing device
US9454437B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 19, 2014 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Nov 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1469
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.