Patent · US Active

Electronic counter in non-volatile limited endurance memory

US9454471B2 · kind B2 · utility

2Cited by
5References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 17, 2013
Grant dateSep 27, 2016
Priority date
Expiry dateFeb 26, 2034

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K21/403
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

An electronic counter is provided having a sequence of memory cells and increment logic. Each memory cell of the sequence is non-volatile and supports a one state and a zero state. The one state can also be referred to as a ‘programmed state’, the zero state as an ‘erased state’. The counter is configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.