Duplicate tag structure employing single-port tag RAM and dual-port state RAM
US9454482B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2013 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Jun 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a single-port memory, a dual-port memory, and a control circuit. The single-port memory may be store tag information associated with a cache memory, and the dual-port memory may be configured to store state information associated with the cache memory. The control circuit may be configured to receive a request which includes a tag address, access the tag and state information stored in the single-port memory and the dual-port memory, respectively, dependent upon the received tag address. A determination of if the data associated with the received tag address is contained in the cache memory may be made the control circuit, and the control circuit may update and store state information in the dual-port memory responsive to the determination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.