Shared global read and write word lines

US9455026B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Niladri Narayan Mojumder · San Diego, US
• Stanley Seungchul Song · San Diego, US
• Zhongze Wang · San Diego, US
• Ping-Lin Liu · Shanghai, CN
• Kern Rim · Yorktown Heights, US
• Choh Fei Yeap · San Diego, US

Key dates

• Filing date: Nov 18, 2014
• Grant date: Sep 27, 2016
• Expiry date: Nov 18, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.