Failure diagnosis circuit
US9455050B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 24, 2015 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Jun 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit generates the second address signal. The addressable module includes addressable components responsive to the address signal. The controller processes the output of the addressable module responsive to the address signal to make a failure diagnosis. The built-in self-test circuit performs signature analysis on the read out output of the addressable module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.