Method and apparatus for mitigating parasitic coupling in a packaged integrated circuit
US9455157B1 · kind B1 · utility
3Cited by
4References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2015 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Sep 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged IC has a package with a die paddle, a signal lead, and a ground lead. The packaged IC also has a die, secured to the package, with a ground pad and a signal pad. The signal pad is electrically connected to the signal lead, and the ground pad is electrically connected to both the die paddle and the ground lead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.