Semiconductor memory device and method of manufacturing semiconductor memory device and method of layouting auxiliary pattern
US9455271B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2015 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Dec 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes a semiconductor substrate, which includes thereon a first region where memory elements are arranged and a second region where circuit elements driving the memory elements are arranged. The first region is provided with a stacked body including a plurality of metal films. Further, the stacked body is divided into a plurality of parts by first separation portions extending in a first direction. The second region is provided with an auxiliary pattern, which includes the stacked body together with a separation portion pair including a pair of second separation portions that divide the stacked body. The second separation portions extend in a second direction intersecting with the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.