Patent · US Active

Manufacturing method of an array substrate

US9455282B2 · kind B2 · utility

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Key dates

Filing dateOct 21, 2014
Grant dateSep 27, 2016
Priority date
Expiry dateOct 21, 2034

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D86/0231

Abstract

Provided is a manufacturing method of an array substrate with an etching stop layer. The method includes: forming a pattern including a gate, a gate line and a common electrode line on a substrate through a first patterning process; forming a gate insulation layer, an active layer film and an etching stop layer through a second patterning process; wherein, the etching stop layer corresponds to a gap between a source and a drain which are to be formed, and a via hole exposing the common electrode line is formed above the common electrode line; forming at least an active layer, a pattern including source, drain and data line and a protection layer through a third patterning process; wherein, the protection layer exposes a part of the drain; and forming at least a pixel electrode through a fourth patterning process; wherein, the pixel electrode is electrically connected with the drain.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.