Power semiconductor device and corresponding module
US9455340B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 2, 2015 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Sep 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/206
Abstract
Power semiconductor device having a wafer, including emitter and collector electrodes arranged on opposite sides, wherein a gate electrode arranged on the emitter side has a conductive gate layer and an insulating layer arranged in the following order between the collector and emitter side: a p doped collector layer, an (n−) doped drift layer, an n doped enhancement layer, a p based base layer having a first and second base region, and an (n+) doped first and second emitter layer, wherein the emitter electrode contacts the first emitter layer and the first base region at an emitter contact area, wherein the second emitter layer is insulated from a direct contact to the emitter electrode by the insulating layer and wherein the second emitter layer is separated from the first emitter layer by the base layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.